As device dimensions scale, the thickness of the gate oxide has been reduced to less than 2 nm. In this thickness regime, surface roughness and non-uniformity have a significant impact on device performance. Shown in FIG. 1 is a typical MOS transistor. As described above, the thickness of the gate dielectric 20 can be less than 2 nm. For most MOS transistors, the gate dielectric 20 will comprise silicon oxide formed on the silicon substrate. The gate electrode 30, the sidewall structures 40, and the drain region 50 and the source region 60 also comprise the MOS transistor. The MOS transistor shown in FIG. 1 can be formed using standard well known processing techniques. In operation, the proper voltages are applied to the gate 30, drain 50, source 60, and substrate regions 10 to form a depletion region 70 and an inversion region 80. The inversion region 80 is formed at the silicon substrate/gate dielectric interface 90 and comprises free carriers. It is the motion of these free carriers in the inversion region 80 from the source 60 to the drain 50 which results in the drain/source current of the transistor. The amount of transistor current which is produced for given applied voltages depends on the rate at which these free carriers flow through the inversion region 80.
Shown in FIG. 2 is a magnified view of the silicon substrate/gate dielectric region for section 100 illustrate in FIG. 1. Here it is shown that the silicon substrate/gate dielectric interface 90 is not smooth but instead comprises surface roughness shown here in the form of steps. The free carriers in the inversion 110 collide with these steps (or surface roughness) in flowing through the inversion region. These collisions impede the flow of carriers 110 and thus reduce the transistor current. These collisions are enhanced in the case of thin gate dielectrics (i.e. less than 2 nm) due to the high electric fields that exist in the inversion layer 80 which forces the free carriers 110 against the interface 90. In addition the presence of the surface roughness introduces non-uniformities in the thickness of the gate dielectric layer 20. These non-uniformities are becoming increasingly important as the thickness of the gate dielectric layer is reduced.
The realization of atomically flat surfaces on a <100> silicon surface is an extremely difficult task that is becoming even more challenging as wafer diameter increases. A method is therefore need to produce atomically flat silicon substrate/gate dielectric interfaces.